Huawei bets on speed over shrinking transistors to sidestep US chip sanctions – Crypto News

* Experts divided on novelty and impact of Huawei’s new chip principle

* Kirin chip launch crucial to gauge potential of its new chip architecture

* Huawei needs new chip design tools to support its ‘breakthrough’, expert says

By Eduardo Baptista and Che Pan

BEIJING, – Huawei’s new chip design principle focused on boosting transmission speed rather than continuing to shrink semiconductors offers a path for China to build cutting-edge chips despite U.S. sanctions, though whether it represents a true breakthrough remains to be seen.

China has been barred since 2019 from importing ASML’s most advanced extreme ultraviolet lithography machines, curbing the ability of its chipmakers to keep up with global leaders like Taiwan’s TSMC in relying on ever-smaller manufacturing processes that make chips more powerful.

For decades, the semiconductor industry has been governed by Moore’s Law – the observation that the number of transistors on a microchip doubles roughly every two years.

Huawei this week unveiled an alternative approach: cutting the time signals take to move through chips and larger computing systems using a principle it calls the Tau Scaling Law.

Its central technique, LogicFolding, aims to arrange logic, analogue and memory circuits in stacked, more tightly connected structures, potentially improving density, efficiency and clock speeds over the next decade.

Proponents see it as a way to extend chip progress as manufacturing advances begin to slow.

“For Huawei, chips face two key constraints. One is inevitable that Moore’s Law will hit a physical ‘wall’ within the next decade,” He Tingbo, the president of Huawei’s semiconductor business, told China’s People’s Daily this week.

“The other is accidental because of the external restrictions that Huawei encountered this ‘wall’ earlier than its peers,” she said, in a likely reference to U.S. sanctions on importing advanced EUV machines.

But others argue that reducing latency has always been part of semiconductor design and that many of the underlying ideas resemble existing work in three-dimensional stacking, advanced packaging and system optimisation.

“This is a breakthrough for Huawei, but it’s not a threat for TSMC,” Nvidia CEO Jensen Huang told reporters in Taipei on Thursday. “TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC’s technology is very advanced.”

In the race to build more powerful computing systems, the chip industry has already embraced advanced packaging technologies that stack chips vertically.

TSMC has been at the forefront with its packaging technology called SoIC, which enables more tightly integrated heterogeneous chiplets to reduce size and improve performance.

Memory chip makers such as SK Hynix and Samsung Electronics also use advanced 3D stacking and packaging technologies to produce multi-layer memory chips, a key component of AI chipsets, and to improve power efficiency and performance.

Huawei believes LogicFolding may actually go beyond the techniques commonly used in 3D integrated circuit stacking, thanks to “very finely and carefully split the critical paths of logic circuits across multiple layers,” according to Liao Heng, chief scientist at Huawei Semiconductor.

But Bernstein analysts cautioned in a note that while stacking multiple chip layers boosts transistor density, it also increases power density and risks overheating chips. Production yields and costs will be another barrier for adoption, they added.

Huawei’s own roadmap also points to those challenges. Huawei’s He said the approach would require new semiconductor design tools suited to folded chip architectures, as well as better ways to manage heat across devices ranging from smartphones to large AI data centres.

“With the methodology of not optimising the area on a chip level, but on a system level based on time, that will dramatically change the capability requirements for the EDA vendors,” said Handel H. Jones, CEO of International Business Strategies, during a panel discussion on Tau Scaling on Tuesday.

Mainstream EDA software produced by vendors like Cadence Design Systems and Synopsys plays a crucial role in creating blueprints for sophisticated semiconductor devices.

Huawei’s most concrete claims centred on a new Kirin smartphone chip that will be launched later this year, which would be the first to use its LogicFolding architecture.

Compared with its earlier single-layer design, the new chip would improve power efficiency by 41%, and raise the chip’s peak operating speed by nearly 13%, Huawei’s He said in a speech on Monday.

Those figures would be significant if achieved at commercial scale. But Huawei did not provide production yield information, cost comparisons or a clear explanation of how the gains would compare with rival chips made using more advanced process nodes.

“There’s nothing concrete that can be independently verified or benchmarked against other players at the moment,” said Lian Jye Su, chief analyst at tech research firm Omdia.

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